The Insight ERC Analyzer validates electrical rules in complex, custom cell circuit designs. It is especially intended for IC design in the areas of Memory, CPU, and large-scale Mixed Signal. These are the circuits that are most prone to circuit design errors that can go undetected in simulation.

• Capacity exceeding hundred-million transistor counts.
• Over-voltage power sneak paths
• Leaky stages due to under-drive
• Conflicts between power domains
• Over / Under fanout
• Keeper vs leakage, Keeper vs set/reset
• Victim / aggressor
• Script interface for automation & custom plugins
• Integrated with Silicon Canvas Laker and Cadence Composer.